The invention relates to microcomputers.
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network, including for example connection to a host microcomputer for use in debugging routines. Such systems are also known in which each of the interconnected microcomputer chips has its own local memory. For speed of communication it is common for bit packets to be transmitted between modules on a chip in a bit parallel format. However problems arise in both power consumption and available pin space in providing for external off-chip communications in the same parallel bit format as that used on-chip. Such microcomputers require access to instructions or code sequences and, for efficient operation, it is desirable for the instructions to be retrievable from locations within the address space of the CPU. One approach described in co-pending European patent application No. 97308517.8 is to provide an on-chip external communication port forming part of the memory address space of the CPU from which instructions may be fetched and which translates between a parallel format on-chip and a less parallel format for off-chip communications.
In a typical microprocessor chip a programmable interrupt controller (PIC) interfaces between external or on-chip devices and the on-chip CPU(s). To allow an interrupt to be forced on to the CPU the chip is provided with interrupt pins, and external hardware must be provided to make contact with those pins.
According to a first aspect of the present invention there is provided a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device and at least one other device; the integrated circuit chip having: an on-chip CPU with a plurality of registers; a communication bus for providing a parallel communication path between the CPU and a first memory local to the CPU; and an external communication port connected to the communication bus, the port having an internal connection to the bus of an internal parallel signal format and an external connection to the external computer device of an external format less parallel than the said internal format, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby: the port may be addressed by execution of an instruction by the CPU; and the external computer device may send to the integrated circuit chip an interrupt signal simulating an interrupt signal from the other device.
According to a second aspect of the present invention there is provided a method for operating a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device and at least one other device; the integrated circuit chip having:, an on-chip CPU with a plurality of registers; a communication bus for providing a parallel communication path between the CPU and a first memory local to the CPU; and an external communication port connected to the communication bus, the port having an internal connection to the bus of an internal parallel signal format and an external connection to the external computer device of an external format less parallel than the said internal format, the port forming part of the memory address space of the CPU from which instructions may be fetched, whereby: the port may be addressed by execution of an instruction by the CPU; the method comprising sending from the external computer device to the integrated circuit chip an interrupt signal simulating an interrupt signal from the other device.
The interrupt signal may be communicated to the CPU via the communication bus.
The interrupt signal may be communicated as a data packet. The packet may include source device specification data which specifies the said other device. The interrupt signal may include destination data which specifies the CPU.
Suitably, on receipt of the interrupt signal the CPU processes the interrupt signal to change the state of the CPU. The CPU suitably has access to memory containing instructions for the CPU to perform processing in dependence on a change of state caused by the said other device. Preferably the instructions define a routine suitable for handling hardware interrupts. The interrupt signal may suitably include trigger mode specification data which specify whether the interrupt is edge or level triggered.
The external computer device may have a second memory local to the external computer device, which is accessible by the CPU through the port. Preferably the external computer device is configurable to send a plurality of interrupt signals to the integrated circuit chip at predetermined times.
The first memory is suitably an external memory for the single integrated circuit chip. Preferably an on-chip cache is also provided on the integrated circuit chip.